Multi-Threaded Mitigation of Radiation-Induced Soft Errors in Bare-Metal Embedded Systems
Empreu sempre aquest identificador per citar o enllaçar aquest ítem
http://hdl.handle.net/10045/105452
Títol: | Multi-Threaded Mitigation of Radiation-Induced Soft Errors in Bare-Metal Embedded Systems |
---|---|
Autors: | Serrano-Cases, Alejandro | Restrepo Calle, Felipe | Cuenca-Asensi, Sergio | Martínez-Álvarez, Antonio |
Grups d'investigació o GITE: | UniCAD: Grupo de investigación en CAD/CAM/CAE de la Universidad de Alicante |
Centre, Departament o Servei: | Universidad de Alicante. Departamento de Tecnología Informática y Computación |
Paraules clau: | Fault tolerance | Reliability | Thread replication | Lock-step | Soft errors | Bare-metal |
Àrees de coneixement: | Arquitectura y Tecnología de Computadores |
Data de publicació: | de febrer-2020 |
Editor: | Springer Nature |
Citació bibliogràfica: | Journal of Electronic Testing. 2020, 36: 47-57. https://doi.org/10.1007/s10836-019-05846-4 |
Resum: | This article presents a software protection technique against radiation-induced faults which is based on a multi-threaded strategy. Data triplication and instructions flow duplication or triplication techniques are used to improve system reliability and thus, ensure a correct system operation. To achieve this objective, a relaxed lockstep model to synchronize the execution of both, redundant threads and variables under protection on different processing units is defined. The evaluation was performed by means of simulated fault injection campaigns in a multi-core ARM system. Results show that despite being considered techniques that imply an evident overhead in memory and instructions (Duplication With Comparison and Re-Execution – DWC-R and Triple Modular Redundancy – TMR), spreading the replicas in different instruction flows not only produce similar results than classic techniques, but also improves the computational and recovery time in presence of soft-errors. In addition, this paper highlights the importance of protecting memory-allocated data, since the instruction flow triplication is not enough to improve the overall system reliability. |
Patrocinadors: | This work was funded by the Spanish Ministry of Economy and Competitiveness and the European Regional Development Fund through the following projects: ‘Evaluación temprana de los efectos de radiación mediante simulación y virtualización. Estrategias de mitigación en arquitecturas de microprocesadores avanzados’, (Ref: ESP2015-68245-C4-3-P, MINECO/FEDER, UE). |
URI: | http://hdl.handle.net/10045/105452 |
ISSN: | 0923-8174 (Print) | 1573-0727 (Online) |
DOI: | 10.1007/s10836-019-05846-4 |
Idioma: | eng |
Tipus: | info:eu-repo/semantics/article |
Drets: | © Springer Science+Business Media, LLC, part of Springer Nature 2019 |
Revisió científica: | si |
Versió de l'editor: | https://doi.org/10.1007/s10836-019-05846-4 |
Apareix a la col·lecció: | INV - UNICAD - Artículos de Revistas |
Arxius per aquest ítem:
Arxiu | Descripció | Tamany | Format | |
---|---|---|---|---|
Serrano-Cases_etal_2020_JElectronTest_final.pdf | Versión final (acceso restringido) | 1,67 MB | Adobe PDF | Obrir Sol·licitar una còpia |
Serrano-Cases_etal_2020_JElectronTest_preprint.pdf | Preprint (acceso abierto) | 390,5 kB | Adobe PDF | Obrir Vista prèvia |
Tots els documents dipositats a RUA estan protegits per drets d'autors. Alguns drets reservats.