Accelerating tool path computing in turning lathe machining

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Title: Accelerating tool path computing in turning lathe machining
Authors: Jimeno-Morenilla, Antonio | Cuenca-Asensi, Sergio | Martínez-Álvarez, Antonio | Sanchez-Romero, Jose-Luis
Research Group/s: Grupo de Investigación en CAD/CAM/CAE de la Universidad de Alicante
Center, Department or Service: Universidad de Alicante. Departamento de Tecnología Informática y Computación
Keywords: Tool path computation acceleration | FPGA technologies
Knowledge Area: Arquitectura y Tecnología de Computadores
Date Created: 2006
Issue Date: 26-Feb-2007
Publisher: IEEE
Citation: JIMENO MORENILLA, Antonio, et al. "Accelerating tool path computing in turning lathe machining". En: SPL'07: 3rd Southern Conference on Programmable Logic. Piscataway, NJ : IEEE, 2007. ISBN 978-1-4244-0606-7, pp. 75-80
Abstract: Tool path generation is one of the most complex problems in Computer Aided Manufacturing. Although some efficient strategies have been developed, most of them are only useful for standard machining. The algorithm called Virtual Digitizing avoids this problem by its own definition but its computing cost is high and make it difficult for being integrated in standard machining in order to adopt the new ISO standard 14649. Presented in the paper there is a Virtual Digitizing architecture that takes the advantages of Reconfigurable Computing (using Field Programmable Gate Arrays) in order to improve the algorithm efficiency. FPGAs are used as low cost and low frequency coprocessor to accelerate the calculation of tool path, meeting the actual restrictions of the Computer Numeric Controls (CNCs) at the same time. A prototype has been implemented to measure the real impact on the total computing time.
Sponsor: IEEE Circuits and Systems Society
URI: http://hdl.handle.net/10045/11573
ISBN: 978-1-4244-0606-7
DOI: 10.1109/SPL.2007.371727
Language: eng
Type: info:eu-repo/semantics/bookPart
Rights: © Copyright 2007 IEEE
Peer Review: si
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