Francés, Jorge, Bleda, Sergio, Gallego, Sergi, Márquez, Andrés, Neipp, Cristian, Beléndez, Augusto
3D SF–FDTD algorithm optimisation on Intel Xeon coprocessor and NVIDIA GPUs
FRANCÉS MONLLOR, Jorge, et al. “3D SF–FDTD algorithm optimisation on Intel Xeon coprocessor and NVIDIA GPUs”. En: CMMSE 2015: Proceedings of the 15th International Conference on Mathematical Methods in Science and Engineering, Rota, Cádiz, Spain, July 6-10, 2015 / ed. J. Vigo-Aguiar. Rota: CMMSE, 2015. ISBN 978-84-617-2230-3, pp. 531-542
URI: http://hdl.handle.net/10045/52625
DOI: 
ISSN: 2312-0177
ISBN: 978-84-617-2230-3
Abstract: 
In this work the split-field finite-difference time-domain method (SF-FDTD) applied to the analysis of two-dimensionally periodic structures is accelerated for Intel Xeon Phi coprocessors and NVIDIA GPUs platforms. The performance achieved by the novel Intel coprocessors is compared with GPU computing and the sequential code optimized by the compiler and parallelized by means of OpenMP in a single CPU with several cores. The results show that in all cases the CUDA version of the 3D SF-FDTD algorithm is more than thirteen times faster compared to the sequential code and until three times faster compared to the Intel Xeon Phi coprocessor. It is worth to note that the speed up obtained by the Intel Xeon Phi coprocessor is achieved using the sequential code of the CPU program since it is based on the Intel Many Integrated Core (MIC) architecture. Therefore, the time costs needed for launching applications on Intel Xeon Phi coprocessors are dramatically reduced compared to the efforts needed for developing CUDA codes compatible with the NVIDIA GPUs.
Keywords:Intel Xeon Phi coprocessor, CUDA, GPU, Fiffite-difference schemes
CMMSE
info:eu-repo/semantics/conferenceObject