3D SF–FDTD algorithm optimisation on Intel Xeon coprocessor and NVIDIA GPUs

Please use this identifier to cite or link to this item: http://hdl.handle.net/10045/52625
Información del item - Informació de l'item - Item information
Title: 3D SF–FDTD algorithm optimisation on Intel Xeon coprocessor and NVIDIA GPUs
Authors: Francés, Jorge | Bleda, Sergio | Gallego, Sergi | Márquez, Andrés | Neipp, Cristian | Beléndez, Augusto
Research Group/s: Holografía y Procesado Óptico
Center, Department or Service: Universidad de Alicante. Departamento de Física, Ingeniería de Sistemas y Teoría de la Señal | Universidad de Alicante. Instituto Universitario de Física Aplicada a las Ciencias y las Tecnología
Keywords: Intel Xeon Phi coprocessor | CUDA | GPU | Fiffite-difference schemes
Knowledge Area: Física Aplicada | Óptica | Teoría de la Señal y Comunicaciones
Date Created: 1-Jun-2015
Issue Date: 6-Jul-2015
Publisher: CMMSE
Citation: FRANCÉS MONLLOR, Jorge, et al. “3D SF–FDTD algorithm optimisation on Intel Xeon coprocessor and NVIDIA GPUs”. En: CMMSE 2015: Proceedings of the 15th International Conference on Mathematical Methods in Science and Engineering, Rota, Cádiz, Spain, July 6-10, 2015 / ed. J. Vigo-Aguiar. Rota: CMMSE, 2015. ISBN 978-84-617-2230-3, pp. 531-542
Abstract: In this work the split-field finite-difference time-domain method (SF-FDTD) applied to the analysis of two-dimensionally periodic structures is accelerated for Intel Xeon Phi coprocessors and NVIDIA GPUs platforms. The performance achieved by the novel Intel coprocessors is compared with GPU computing and the sequential code optimized by the compiler and parallelized by means of OpenMP in a single CPU with several cores. The results show that in all cases the CUDA version of the 3D SF-FDTD algorithm is more than thirteen times faster compared to the sequential code and until three times faster compared to the Intel Xeon Phi coprocessor. It is worth to note that the speed up obtained by the Intel Xeon Phi coprocessor is achieved using the sequential code of the CPU program since it is based on the Intel Many Integrated Core (MIC) architecture. Therefore, the time costs needed for launching applications on Intel Xeon Phi coprocessors are dramatically reduced compared to the efforts needed for developing CUDA codes compatible with the NVIDIA GPUs.
Sponsor: This work was supported by the “Ministerio de Economía y Competitividad” of Spain under project FIS2011-29803-C02-01, by the “Generalitat Valenciana” of Spain under projects ISIC/2012/013 and GV/2014/076, and by the "Universidad de Alicante" of Spain under project
URI: http://hdl.handle.net/10045/52625
ISBN: 978-84-617-2230-3
ISSN: 2312-0177
Language: eng
Type: info:eu-repo/semantics/conferenceObject
Rights: © CMMSE
Peer Review: si
Publisher version: http://cmmse.usal.es/cmmse2015/
Appears in Collections:INV - GHPO - Comunicaciones a Congresos, Conferencias, etc.

Files in This Item:
Files in This Item:
File Description SizeFormat 
Thumbnail15thCMMSE_Rota_pp531-542_2015.pdf1,5 MBAdobe PDFOpen Preview

Items in RUA are protected by copyright, with all rights reserved, unless otherwise indicated.