Time-Precision Flexible Adder

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Title: Time-Precision Flexible Adder
Authors: García-Chamizo, Juan Manuel | Mora Pascual, Jerónimo Manuel | Mora, Higinio
Research Group/s: Informática Industrial y Redes de Computadores
Center, Department or Service: Universidad de Alicante. Departamento de Tecnología Informática y Computación
Keywords: Application specific architectures | Look-up tables | Specialized architecture | Adder
Knowledge Area: Arquitectura y Tecnología de Computadores
Issue Date: 2003
Publisher: IEEE
Citation: Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003. Vol. 3. IEEE, 2003. ISBN 0-7803-8163-7, pp. 994-997
Abstract: A new conception of flexible calculation that allows us to adjust a sum depending on the available time computation is presented. More specifically, the objective is to obtain a calculation model that makes the processing time/precision more flexible. The addition method is based on carry-select scheme adder and the proposed design uses precalculated data stored in look-up tables, which provide, above all, quality results and systematization in the implementation of low level primitives that set parameters for the processing time. We report an evaluation of the architecture in area, delay and computation error, as well as a suitable implementation in FPGA to validate the design.
Description: Paper submitted to 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sharjah, Emiratos Árabes, 2003.
Sponsor: This work is being backed by grant DPI2002-04434-C04-01 from the Ministerio de Ciencia y Tecnología of the Spanish Government.
URI: http://hdl.handle.net/10045/45454
ISBN: 0-7803-8163-7
DOI: 10.1109/ICECS.2003.1301676
Language: eng
Type: info:eu-repo/semantics/conferenceObject
Rights: © 2003 IEEE
Peer Review: si
Publisher version: http://dx.doi.org/10.1109/ICECS.2003.1301676
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