Parametrizable Architecture for Function Recursive Evaluation

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Title: Parametrizable Architecture for Function Recursive Evaluation
Authors: García-Chamizo, Juan Manuel | Signes Pont, María Teresa | Mora, Higinio | Miguel Casado, Gregorio de
Research Group/s: Informática Industrial y Redes de Computadores
Center, Department or Service: Universidad de Alicante. Departamento de Tecnología Informática y Computación
Keywords: Convolution | Function evaluation | FPGA | Serial-distributed arithmetic
Knowledge Area: Arquitectura y Tecnología de Computadores
Issue Date: 2003
Abstract: This paper presents a function evaluation method developed under the scope of recursive expression of function convolution. This approach is based on a unique parametrizable formula capable of providing function points by successive iteration. When tackling design level, it also shows suitable for developing architectural schemes capable of dealing with different speed and precision issues. An architecture for reconfigurable FPGA based in serial distributed arithmetic implements the design for fast prototyping. The case of combined trigonometric functions involved in rotation is analyzed under this scope. Compared with others methods, our proposal offers a good balance between speed and precision.
Description: Paper submitted to the XVIII Conference on Design of Circuits and Integrated Systems (DCIS), Ciudad Real, España, 2003.
Language: eng
Type: info:eu-repo/semantics/conferenceObject
Rights: Licencia Creative Commons Reconocimiento-NoComercial-SinObraDerivada 4.0
Peer Review: si
Appears in Collections:INV - I2RC - Comunicaciones a Congresos, Conferencias, etc.
INV - AIA - Comunicaciones a Congresos, Conferencias, etc.

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